Cadence Adds Major Enhancements to Its Market Leading Signal Processing Worksystem

SPW 4.8 Strengthens Vision for Design and Development of Algorithmic-Intensive DSP and Communications Systems

PARIS--(BUSINESS WIRE)--March 5, 2002-- Cadence Design Systems, Inc. (NYSE: CDN - news), the world's leading supplier of electronic design products and services, today announced a substantial upgrade to its Signal Processing Worksystem (SPW). SPW is the industry's first system-level, hierarchical block diagram design solution with an optimized flow for implementation. It helps manage the complexity of today's communications and multimedia designs by giving hardware, software, and RF engineers a means to collaborate on their projects, which can significantly reduce design time and risk.

SPW 4.8 incorporates a broad spectrum of new capabilities and enhancements to both the core system and its links with other tools. These include tight integrations with the Xilinx Coregen solution, with the analog design flow that supports the Cadence® AMS Designer, and with SystemC 2.0. SPW 4.8 users can enter and simulate designs consisting of various types of models including C, C++, Verilog, VHDL, Verilog-AMS, SystemC, ISS, and Matlab. SPW 4.8 also supports server farms on HP-UX, Solaris, and Linux platforms to accelerate bit error rate (BER) simulations studies.

"SPW is a versatile tool for our wireless designs. To ensure on-time silicon delivery, which is critical to us, we leverage several SPW features including reference testbenches for wireless standards and fixed-point simulation for algorithm-to-ASIC test vector generation," said Murali Krishnan, Senior Member of the Technical Staff, Systems Architecture, Morphics Technology. "The system and its associated libraries for 3G and other wireless standards have proven to be an ideal platform for launching our algorithmic exploration. The pre-verified modules in HDS enable rapid capture of fixed-point versions of algorithms and test vector generation for complex designs. The Linux support in SPW4.8 operates seamlessly and makes it possible to utilize the compute power available on gigahertz PCs."

"SPW has long been the benchmark in the system-level design space for good reason," said Rahul Razdan, corporate vice president and general manager of Systems and Functional Verification at Cadence. "We continue to optimize this product to address the needs of today's design engineers who are working with complex SoC and multi-ASIC/FPGA designs, especially in the advanced digital communications and multimedia markets. The structure of SPW -- from the core system, to its links with other tools, to its best-in-class libraries -- is intended to reduce cost and speed time to market."

The integration of SPW with Xilinx Coregen blocks creates a powerful front-end solution that offers both a complete flow from system-level to hardware design and the ability to take advantage of Xilinx's optimized cores within the SPW environment. With SPW 4.8, users can utilize Xilinx Coregen blocks and directly validate them against the algorithmic description before they take the entire design to Xilinx place and route.

The tight integration SPW 4.8 has with SystemC 2.0 -- through Block Wizard -- accelerates reuse of models written in an industry-standard modeling language, as well as models customers have written in SPW and its rich set of libraries. As customers add custom blocks using SystemC, the tight integration of the debug environment makes it much easier to locate design problems, thus reducing time to market.

A new solution also available with SPW 4.8 is a tight integration with the analog design flow that supports Cadence AMS designer. This allows RF engineers to validate transceiver circuits together with the digital design before building a prototype, which leads to more stable designs that are easier and less costly to manufacture.

Simulation studies are accelerated through the SPW 4.8's LSF support of server farms that run on HP-UX, Solaris, and Linux platforms. This meets the needs of complex systems that require substantial parameter studies to ensure that performance requirements can be met under all conditions.

SPW 4.8 also accelerates BER simulation studies -- which typically consume days -- by splitting up the run and combining the results, thus cutting validation time almost linearly with the computer resources that are added.

"We used the SPW environment for the elaboration and test of prototypes with the goal of demonstrating the functionality of DECT or Bluetooth radio architectures," said Emmanuel Brunel, RF System Engineer, Bluetooth Core Competency, Philips Consumer Electronics in Le Mans, France. "We started by developing and validating a radio architecture using floating-point models in a system-level simulation. The modules of interest for the demonstration, which were part of the radio back-end, were translated in VHDL using the NC-Sim environment. Then, the SPW-HDS link with the seamless connection to NC-Sim allowed us to perform the verification of each sub-system translated in VHDL. The validated VHDL models were synthesized and programmed in a FPGA for a complete hardware-level evaluation and are now usable for any communication circuit design. The process of co-simulation -- performed in a single environment -- led to a significant reduction in design time."

Several other new productivity capabilities have also been added to SPW 4.8, such as hierarchical access to parameters. The link to data path synthesis has been significantly improved in the area of general arithmetic blocks and additional blocks being mapped to AmbitWare/DesignWare components for a more automated, optimized path to hardware implementation. When looking at simulation speed, block profiling capabilities are particularly useful because they indicate where most run time is spent in a design. Because SPW now collaborates with other tools and environments it also includes Stream Management which reduces the risk of incompatibility between various tools by managing all environment and path settings.

Price and Availability

Available immediately, the SPW 4.8 signal processing worksystem is priced at $22,000 for a one-year license. SPW 4.8 supports the Forte 6 Update1 compiler running on Sun Solaris 2.7 and 2.8, and requires a C++ A.03.31 compiler on HP-UX 11 platforms. In addition, simulations are supported on low-cost Linux Redhat 7.0 platforms and require a GCC g++2.96 compiler.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,700 employees and 2001 revenues of approximately $1.43 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif. and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at http://www.cadence.com.

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

     Cadence Design Systems, Inc.
     Valerie J. Smith, 408/428-5795
     vsmith@cadence.com